With advances in technologies and device scaling, integrated circuit chip designs incorporate an increasingly large number of embedded memories (also referred to herein as embedded memory arrays) as well as built-in self-test (BIST) circuits for testing such embedded memories, when operating in a test mode (as opposed to a functional mode). Oftentimes an integrated circuit chip design will incorporate multiple BIST engines controlled by a BIST controller and each BIST engine will test multiple embedded memories of the same specific type (e.g., multiple static random access memory arrays (SRAMs), multiple dynamic random access memory arrays (DRAMs), etc.) in parallel.
In this case, the BIST engine has an address generator and a test pattern generator. The address generator generates multiple test addresses and, specifically, generates test addresses corresponding to all addresses in a maximum possible address space, which is associated with the specific type of memory under test and equal to a maximum number of banks in the memory multiplied by a maximum number of word lines per bank multiplied by a maximum decode number per data bit column. The test pattern generator generates test patterns to be applied to these test addresses in the memories under test. Then, the BIST engine sweeps through the address space of each memory, writing the test patterns to the test addresses. The output is then read and analyzed by comparison logic in an input/output interface, which allows for communication between the BIST engine and a corresponding memory under test, in order to confirm that the memory cells at the various test addresses in that corresponding memory are functioning properly.
Oftentimes, however, the memories tested by a given BIST engine may have address spaces that are less than the maximum possible address space associated with the specific type of memory under test and, specifically, may have a lesser number of banks than the predetermined maximum number of banks, a lesser number of word lines per bank than the predetermined maximum number of word lines per bank and/or a lesser decode number per data bit column than the predetermined maximum decode number per data bit column. To accommodate the overabundance of test addresses generated by the BIST engine in such cases and to enable in parallel testing of memories of different sizes (i.e., in parallel testing of memories with different total address spaces), each input/output interface block connected between the BIST engine and a corresponding memory is typically configured to sort in-range test addresses (i.e., test addresses that are received from the BIST engine and that are within the address space for the corresponding memory) from out-of-range test addresses (i.e., test addresses that are received from the BIST engine and that are above the address space for the corresponding memory). Although testing of memories of different sizes can be performed by such BIST circuits, sweeping the maximum possible address space can be a significant waste of time, particularly, when relatively small memories are tested.